Monday, December 24, 2007

How IDL cannot handle logical AND operation?

if n_elements(ispressed) ne 0 and ispressed eq 1 then begin

If the variable ispressed is not defined, then the program will stop and give a error message,
% Variable is undefined: ISPRESSED.
% Execution halted at: ... ...

But, in my memory, if the left part of AND is false, the right part will not be evaluated. Does IDL behave differently?

1 comment:

Anonymous said...

OMG. I mistaked AND and && for such a long time. The AND is a bitwise operator, while && is a logical operator. I can't believe I did such a foolish thing in such long time. God. Who am I?